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FEATURES Superb Clamping Characteristics 3 mV Clamp Error 1.5 ns Overdrive Recovery Minimized Nonlinear Clamping Region 240 MHz Clamp Input Bandwidth 3.9 V Clamp Input Range Wide Bandwidth AD8036 AD8037 Small Signal 240 MHz 270 MHz Large Signal (4 V p-p) 195 MHz 190 MHz Good DC Characteristics 2 mV Offset 10 V/ C Drift Ultralow Distortion, Low Noise -72 dBc typ @ 20 MHz 4.5 nV/Hz Input Voltage Noise High Speed Slew Rate 1500 V/ s Settling 10 ns to 0.1%, 16 ns to 0.01% 3 V to 5 V Supply Operation APPLICATIONS ADC Buffer IF/RF Signal Processing High Quality Imaging Broadcast Video Systems Video Amplifier Full Wave Rectifier PRODUCT DESCRIPTION
Low Distortion, Wide Bandwidth Voltage Feedback Clamp Amps AD8036/AD8037
FUNCTIONAL BLOCK DIAGRAM 8-Lead Plastic DIP (N), Cerdip (Q), and SO Packages
NC -INPUT +INPUT -VS 1 2 3 4
(Top View) NC = NO CONNECT
AD8036/ AD8037
8 7 6 5
VH +VS OUTPUT VL
and large-signal bandwidths and ultralow distortion. The AD8036 achieves -66 dBc at 20 MHz, and 240 MHz smallsignal and 195 MHz large-signal bandwidths. The AD8036 and AD8037's recover from 2x clamp overdrive within 1.5 ns. These characteristics position the AD8036/AD8037 ideally for driving as well as buffering flash and high resolution ADCs. In addition to traditional output clamp amplifier applications, the input clamp architecture supports the clamp levels as additional inputs to the amplifier. As such, in addition to static dc clamp levels, signals with speeds up to 240 MHz can be applied to the clamp pins. The clamp values can also be set to any value within the output voltage range provided that VH is greater that VL . Due to these clamp characteristics, the AD8036 and AD8037 can be used in nontraditional applications such as a full-wave rectifier, a pulse generator, or an amplitude modulator. These novel applications are only examples of some of the diverse applications which can be designed with input clamps. The AD8036 is offered in chips, industrial (-40C to +85C) and military (-55C to +125C) package temperature ranges and the AD8037 in industrial. Industrial versions are available in plastic DIP and SOIC; MIL versions are packaged in cerdip.
4 AD8036 3 OUTPUT VOLTAGE - Volts 2 1 0 VL = -1V -1 -2 -3 VL = -2V VL = -3V VH = 3V VH = 2V VH = 1V
The AD8036 and AD8037 are wide bandwidth, low distortion clamping amplifiers. The AD8036 is unity gain stable. The AD8037 is stable at a gain of two or greater. These devices allow the designer to specify a high (VCH) and low (VCL ) output clamp voltage. The output signal will clamp at these specified levels. Utilizing a unique patent pending CLAMPINTM input clamp architecture, the AD8036 and AD8037 offer a 10x improvement in clamp performance compared to traditional output clamping devices. In particular, clamp error is typically 3 mV or less and distortion in the clamp region is minimized. This product can be used as a classical op amp or a clamp amplifier where a high and low output voltage are specified. The AD8036 and AD8037, which utilize a voltage feedback architecture, meet the requirements of many applications which previously depended on current feedback amplifiers. The AD8036 and AD8037 exhibit an exceptionally fast and accurate pulse response (16 ns to 0.01%), extremely wide small-signal
CLAMPIN is a trademark of Analog Devices, Inc.
-4 -4
-3
-2
-1 0 1 INPUT VOLTAGE - Volts
2
3
4
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1. Clamp DC Accuracy vs. Input Voltage
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD8036/AD8037-SPECIFICATIONS100 ; A = +1 (AD8036); A = +2 (AD8037), V , V open, unless (V = 5 V; R =
ELECTRICAL CHARACTERISTICS otherwise noted)
Parameter DYNAMIC PERFORMANCE Bandwidth (-3 dB) Small Signal Large Signal 1 Bandwidth for 0.1 dB Flatness Slew Rate, Average +/- Rise/Fall Time Settling Time To 0.1% To 0.01% HARMONIC/NOISE PERFORMANCE 2nd Harmonic Distortion 3rd Harmonic Distortion 3rd Order Intercept Noise Figure Input Voltage Noise Input Current Noise Average Equivalent Integrated Input Noise Voltage Differential Gain Error (3.58 MHz) Differential Phase Error (3.58 MHz) Phase Nonlinearity CLAMP PERFORMANCE Clamp Voltage Range 2 Clamp Accuracy Clamp Nonlinearity Range3 Clamp Input Bias Current (VH or VL) Clamp Input Bandwidth (-3 dB) Clamp Overshoot Overdrive Recovery DC PERFORMANCE 4, RL = 150 Input Offset Voltage 5 Offset Voltage Drift Input Bias Current TMIN -TMAX Input Offset Current Common-Mode Rejection Ratio Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Range, R L = 150 Output Current Output Resistance Short Circuit Current POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio TMIN -TMAX TMIN -TMAX 3.2 TMIN -TMAX VCM = 2 V VOUT = 2.5 V TMIN -TMAX 66 48 40 0.3 90 55 Conditions
S LOAD V V H L
AD8036A Min Typ Max
AD8037A Min Typ Max
Units
VOUT 0.4 V p-p 150 8036, VOUT = 2.5 V p-p; 8037, VOUT = 3.5 V p-p 160 VOUT 0.4 V p-p 8036, RF = 140 ; 8037, R F = 274 VOUT = 4 V Step, 10-90% 900 VOUT = 0.5 V Step, 10-90% VOUT = 4 V Step, 10-90% VOUT = 2 V Step VOUT = 2 V Step 2 V p-p; 20 MHz, RL = 100 RL = 500 2 V p-p; 20 MHz, RL = 100 RL = 500 25 MHz RS = 50 1 MHz to 200 MHz 1 MHz to 200 MHz 0.1 MHz to 200 MHz RL = 150 RL = 150 DC to 100 MHz VCH or V CL 2x Overdrive, V CH = +2 V, VCL = -2 V TMIN-TMAX 8036, VH, L = 1 V; 8037, VH, L = 0.5 V TMIN-TMAX VCH or V CL = 2 V p-p 2x Overdrive, V CH or V CL = 2 V p-p 2x Overdrive 3.3
240 195 130 1200 1.4 2.6 10 16 -59 -66 -68 -72 +46 18 6.7 2.2 95 0.05 0.02 1.1 3.9 3 100 40 -52 -59 -61 -65
200 160
270 190
MHz MHz MHz V/s ns ns ns ns -45 -65 -63 -73 dBc dBc dBc dBc dBm dB nVHz pAHz V rms % Degree Degree V mV mV mV A A MHz % ns mV mV V/C A A A A dB dB dB k pF V V mA mA V mA mA dB
130 1100 1500 1.2 2.2 10 16 -52 -72 -70 -80 +41 14 4.5 2.1 60 0.02 0.02 1.1
0.09 0.04
0.04 0.04
10 20 60 80 5
150
240 1 1.5 2
3.3 3.9 3 10 20 100 50 70 90 180 270 1 5 1.3 2 10 3 0.1 70 54 46 90 60 7 10 9 15 3 5
TMIN -TMAX
10 4
7 11 10 15 3 5
500 1.2 2.5 3.9 70 0.3 240 5.0 20.5 60 6.0 21.5 25
500 1.2 2.5 3.2 3.9 70 0.3 240 3.0 5.0 6.0 18.5 19.5 24 56 66
3.0
50
NOTES 1 See Max Ratings and Theory of Operation sections of data sheet. 2 See Max Ratings. 3 Nonlinearity is defined as the voltage delta between the set input clamp voltage (VH or V L) and the voltage at which V OUT starts deviating from VIN (see Figure 73). 4 Measured at A V = 50. 5 Measured with respect to the inverting input. Specifications subject to change without notice.
-2-
REV. A
AD8036/AD8037
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V Voltage Swing x Bandwidth Product . . . . . . . . . . . 350 V-MHz |VH-VIN| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 V |VL-VIN| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 V Internal Power Dissipation2 Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . . 1.3 Watts Small Outline Package (SO) . . . . . . . . . . . . . . . . . . 0.9 Watts Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range N, R . . . . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead Plastic DIP: JA = 90C/W 8-Lead SOIC: JA = 155C/W 8-Lead Cerdip: JA = 110C/W.
The maximum power that can be safely dissipated by these devices is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately +150C. Exceeding this limit temporarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of +175C for an extended period can result in device failure. While the AD8036 and AD8037 are internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (+150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0 MAXIMUM POWER DISSIPATION - Watts 8-LEAD PLASTIC DIP PACKAGE TJ = +150 C
1.5
1.0
METALIZATION PHOTO
Dimensions shown in inches and (mm). Connect Substrate to -VS .
-IN VH 8 +VS 7
0.5
8-LEAD SOIC PACKAGE
2
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
0.046 (1.17)
70
80 90
6
OUT
Figure 2. Plot of Maximum Power Dissipation vs. Temperature
ORDERING GUIDE
3
4
5
8036
AD8036
+VS 7
Model AD8036AN AD8036AR AD8036AR-REEL AD8036AR-REEL7 AD8036ACHIPS AD8036-EB 5962-9559701MPA AD8037AN AD8037AR AD8037AR-REEL AD8037AR-REEL7 AD8037ACHIPS AD8037-EB
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description
Package Option N-8 SO-8 SO-8 SO-8
+IN
-VS
VL 0.050 (1.27)
-IN 2
VH 8
Plastic DIP SOIC 13" Tape and Reel 7" Tape and Reel Die Evaluation Board -55C to +125C Cerdip Plastic DIP SOIC 13" Tape and Reel 7" Tape and Reel Die Evaluation Board
Q-8 N-8 SO-8 SO-8 SO-8
0.046 (1.17)
6
OUT
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
3
4
5
8037
AD8037
+IN
-VS
VL 0.050 (1.27)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although these devices feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
-3-
AD8036/AD8037 AD8036-Typical Characteristics
RF 10 F PULSE GENERATOR T R /T F = 350ps 130 VIN 49.9 RF 10 F +VH 0.1 F +VS 0.1 F +VS PULSE GENERATOR T R /T F = 350ps
0.1 F
AD8036
0.1 F 10 F -VS
VOUT RL = 100 VIN 49.9
130
AD8036
0.1 F
VOUT RL = 100
0.1 F VL -VS
10 F
Figure 3. Noninverting Configuration, G = +1
Figure 6. Noninverting Clamp Configuration, G = +1
Figure 4. Large Signal Transient Response; VO = 4 V p-p, G = +1, RF = 140
Figure 7. Clamped Large Signal Transient Response (2x Overdrive); VO = 2 V p-p, G = +1, R F = 140 , V H = +1 V, VL = -1 V
Figure 5. Small Signal Transient Response; VO = 400 mV p-p, G = +1, RF = 140
Figure 8. Clamped Small Signal Transient Response (2x Overdrive); VO = 400 mV p-p, G = +1, RF = 140 , VH = +0.2 V, VL = -0.2 V
-4-
REV. A
AD8036/AD8037 AD8037-Typical Characteristics
RF PULSE GENERATOR T R /T F = 350ps RIN 10 F PULSE GENERATOR T R /T F = 350ps RIN +VH 0.1 F +VS 0.1 F RF 10 F +VS
0.1 F
100 VIN 49.9
AD8037
0.1 F 10 F -VS
VOUT RL = 100 VIN 49.9
100
AD8037
0.1 F
VOUT RL = 100
0.1 F VL -VS
10 F
Figure 9. Noninverting Configuration, G = +2
Figure 12. Noninverting Clamp Configuration, G = +2
Figure 10. Large Signal Transient Response; VO = 4 V p-p, G = +2, RF = RIN = 274
Figure 13. Clamped Large Signal Transient Response (2x Overdrive); VO = 2 V p-p, G = +2, RF = RIN = 274 , VH = +0.5 V, VL = -0.5 V
Figure 11. Small Signal Transient Response; VO = 400 mV p-p, G = +2, RF = RIN = 274
Figure 14. Clamped Small Signal Transient Response (2x Overdrive); VO = 400 mV p-p, G = +2, RF = RIN = 274 , VH = +0.1 V, VL = -0.1 V
REV. A
-5-
AD8036/AD8037 AD8036-Typical Characteristics
2 1 0 -1 GAIN - dB -2 -3 -4 -5 -6 -7 -8 1M 200 20 40 60 80 100 120 140 160 180 200 VALUE OF FEEDBACK RESISTOR (RF) - 220 240 VO = 300mV p-p VS = 5V RL = 100 200 140 -3dB BANDWIDTH - MHz 350 VS = 5V RL = 100 GAIN = +1 N PACKAGE 300 400 RF
130 49.9
AD8036 RL
102 49.9
250
R PACKAGE
10M 100M FREQUENCY - Hz
1G
Figure 15. AD8036 Small Signal Frequency Response, G = +1
0.2 0.1 0 -0.1 GAIN - dB -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M 100M FREQUENCY - Hz 1G VO = 300mV p-p VS = 5V RL = 100 140 158 150
Figure 18. AD8036 Small Signal -3 dB Bandwidth vs. RF
2 1 0 -1 OUTPUT - dB -2 -3 -4 -5 -6 -7 -8 1M 10M 100M FREQUENCY - Hz 1G RF = 50 TO 250 BY 50 VS = 5V VO = 2.5V p-p RL = 100 50 250
130
Figure 16. AD8036 0.1 dB Flatness, N Package (for R Package Add 20 to RF)
90 80 70 PHASE OPEN -LOOP GAIN - dB 60 50 40 30 20 10 0 -10 -20 10k 100k 1M 10M FREQUENCY - Hz 100M GAIN 40 20 0 -20 -40 -60 -80 -100 -120 1G 100 80 60 PHASE MARGIN - Degrees
Figure 19. AD8036 Large Signal Frequency Response, G = +1
2 1 0 -1 GAIN - dB -2 -3 -4 -5 -6 -7 -8 100k 1M 1V AD8036 100 VH VL (VIN) 10M FREQUENCY - Hz 100M 1G (VO) VS = 5V VO = 300mV p-p RL = 100 140
Figure 17. AD8036 Open-Loop Gain and Phase Margin vs. Frequency, RL = 100
Figure 20. AD8036 Clamp Input Bandwidth, VH, VL
-6-
REV. A
AD8036/AD8037
-30
0.06 DIFF GAIN - % 0.04 0.02 0.00 -0.02 -0.04 -0.06 1st
2ND HARMONIC VO = 2V p-p VS = 5V RL = 500 G = +1
HARMONIC DISTORTION - dBc
-50
-70
2nd
3rd
4th
5th
6th
7th
8th
9th 10th 11th
-90
DIFF PHASE - Degrees
0.04 0.02 0.00 -0.02 -0.04 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
-110
3RD HARMONIC
-130 10k
100k
1M FREQUENCY - Hz
10M
100M
Figure 21. AD8036 Harmonic Distortion vs. Frequency, RL = 500
Figure 24. AD8036 Differential Gain and Phase Error, G = +1, RL = 150 , F = 3.58 MHz
-30 VO = 2V p-p VS = 5V RL = 100 G = +1 2ND HARMONIC
0.05 0.04 0.03 0.02
HARMONIC DISTORTION - dBc
-50
ERROR - %
3RD HARMONIC
-70
0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
-90
-110
-130 10k
100k
1M FREQUENCY - Hz
10M
100M
0
5
10 15 20 25 30 SETTLING TIME - ns
35
40
45
Figure 22. AD8036 Harmonic Distortion vs. Frequency, RL = 100
Figure 25. AD8036 Short-Term Settling Time to 0.01%, 2 V Step, G = +1, RL = 100
60
0.4 0.3 0.2
50 INTERCEPT - +dBm
0.1
ERROR - %
0 -0.1 -0.2 -0.3
40
30
-0.4 -0.5 -0.6
20 10
0
2
20
40 FREQUENCY - MHz
60
80
100
4 6 8 10 12 14 SETTLING TIME - s
16
18
Figure 23. AD8036 Third Order Intercept vs. Frequency
Figure 26. AD8036 Long-Term Settling Time, 2 V Step, G = +1, RL = 100
REV. A
-7-
AD8036/AD8037 AD8037-Typical Characteristics
8 475 7 6 -3dB BANDWIDTH - MHz 5 GAIN - dB 4 3 2 1 0 -1 -2 1M 10M 100M FREQUENCY - Hz 1G 150 100 150 200 250 300 350 400 VALUE OF RF,RIN - 450 500 550 VO = 300mV p-p VS = 5V RL = 100 274 174 300 374 350 VS = 5V RL = 100 GAIN = +2 49.9 RIN 100 RF AD8037 RL
250 R PACKAGE N PACKAGE
200
Figure 27. AD8037 Small Signal Frequency Response, G = +2
Figure 30. AD8037 Small Signal -3 dB Bandwidth vs. RF, RIN
0.2 0.1 0 -0.1 GAIN - dB -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1M 10M 100M FREQUENCY - Hz VO = 3.00mV p-p VS = 5V RL = 100 301
8 7 RF = 475
274 249 224 GAIN - dB
6 5 4 3 2 1 0 -1 VO = 3.5 V p-p VS = 5V RL = 100 RF = 75
RF = 75 TO 475 BY 100
1G
-2 1M
10M 100M FREQUENCY - Hz
1G
Figure 28. AD8037 0.1 dB Flatness, N Package (for R Package Add 20 to RF)
Figure 31. AD8037 Large Signal Frequency Response, G = +2
65 60 55 50 OPEN -LOOP GAIN - dB 45 40 35 30 25 20 15 10 5 0 GAIN 100 PHASE 50 0 -50 -100 -150 -200 -250 1G PHASE MARGIN - Degrees
8 7 6 5 GAIN - dB 4 3 2 1 0 -1 -2 100k 1V 274 AD8037 100 VH VL (VIN) 1M 10M FREQUENCY - Hz 100M 1G (VO) VS = 5V VO = 300mV p-p RL = 100 274
-5 -10 -15 10k 100k 1M 10M FREQUENCY - Hz 100M
Figure 29. AD8037 Open-Loop Gain and Phase Margin vs. Frequency, RL = 100
Figure 32. AD8037 Clamp Input Bandwidth, VH, VL
-8-
REV. A
AD8036/AD8037
-30 VO = 2V p-p VS = 5V RL = 500 G = +2 DIFF GAIN - % 2ND HARMONIC DIFF PHASE - Degrees -90 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.03 0.02 0.01 0.00 -0.01 -0.02 -0.03 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
HARMONIC DISTORTION - dBc
-50
-70
-110
3RD HARMONIC
-130 10k
100k
1M FREQUENCY - Hz
10M
100M
Figure 33. AD8037 Harmonic Distortion vs. Frequency, R L = 500
Figure 36. AD8037 Differential Gain and Phase Error G = +2, RL = 150 , F = 3.58 MHz
-30 -0.05 HARMONIC DISTORTION - dBc VO = 2V p-p VS = 5V RL = 100 G = +2 -0.04 2ND HARMONIC -0.03 -0.02 ERROR - % 100M -0.01 0 -0.01 -0.02 -110 -0.03 -0.04 -130 10k -0.05 100k 1M FREQUENCY - Hz 10M 0 5 10 15 20 25 30 SETTLING TIME - ns 35 40 45
-50
-70
-90
3RD HARMONIC
Figure 34. AD8037 Harmonic Distortion vs. Frequency, RL = 100
Figure 37. AD8037 Short-Term Settling Time to 0.01%, 2 V Step, G = +2, RL = 100
60
0.4 0.3 0.2
50 INTERCEPT - +dBm ERROR - %
0.1 0 -0.1 -0.2 -0.3
40
30
-0.4 -0.5 -0.6
20 10
20
40 FREQUENCY - MHz
60
80
100
0
2
4 6 8 10 12 14 SETTLING TIME - s
16
18
Figure 35. AD8037 Third Order Intercept vs. Frequency
Figure 38. AD8037 Long-Term Settling Time 2 V Step, RL = 100
REV. A
-9-
AD8036/AD8037-Typical Characteristics
32 17 INPUT NOISE VOLTAGE - nV/ Hz INPUT NOISE VOLTAGE - nV/ Hz 28 VS = 24 20 16 12 5V 15 VS = 13 5V
11
9 7
8 4 10
5 3 10
100
1k FREQUENCY - Hz
10k
100k
100
1k FREQUENCY - Hz
10k
100k
Figure 39. AD8036 Noise vs. Frequency
Figure 42. AD8037 Noise vs. Frequency
PSRR - dB
40 35 30 25 20 15 10 5 0 10k
PSRR - dB
80 75 70 65 60 55 50 45
-PSRR +PSRR
100k
1M 10M FREQUENCY - Hz
100M
1G
80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10k
-PSRR
+PSRR
100k
1M 10M FREQUENCY - Hz
100M
1G
Figure 40. AD8036 PSRR vs. Frequency
Figure 43. AD8037 PSRR vs. Frequency
100 90 80 CMRR - dB CMRR - dB 70 60 50 40 30 20 100k VS = 5V VCM = 1V RL = 100
100 90 80 70 60 50 40 30 1M 10M FREQUENCY - Hz 100M 1G 20 100k VS = 5V VCM = 1V RL = 100
1M
10M FREQUENCY - Hz
100M
1G
Figure 41. AD8036 CMRR vs. Frequency
Figure 44. AD8037 CMRR vs. Frequency
-10-
REV. A
AD8036/AD8037
1k
1400 1300
100
VS = 5V G = +1 OPEN -LOOP GAIN - V/ V
1200 1100
AD8037
1000 900
10 ROUT -
+AOL -AOL
1
800 700 600 500
0.1
AD8036
+AOL -AOL
0.01 0.1M
1.0M
10M FREQUENCY - Hz
100M
300M
400 -60
-40
-20
0
20
40
60
80
100
120
140
JUNCTION TEMPERATURE - C
Figure 45. AD8036 Output Resistance vs. Frequency
Figure 48. Open-Loop Gain vs. Temperature
1k
74 72 70 +PSRR PSRR - dB -PSRR AD8037
100
VS = 5V G = +2
10 ROUT -
68 AD8037 66 64 -PSRR AD8036 +PSRR
1
0.1 62 AD8036 0.01 0.1M 1.0M 10M FREQUENCY - Hz 100M 300M 60 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE - C 120 140
Figure 46. AD8037 Output Resistance vs. Frequency
Figure 49. PSRR vs. Temperature
4.2 4.1 +VOUT OUTPUT SWING - Volts 4.0 -VOUT CMRR - dB 3.9 3.8 3.7 3.6 +VOUT 3.5 -VOUT 3.4 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE - C 120 RL= 50 140 RL=150
96 VCM = 2V 95 94 93 92 91 90 89 88 15
25
35 45 55 65 75 JUNCTION TEMPERATURE - C
85
95
Figure 47. AD8036/AD8037 Output Swing vs. Temperature
Figure 50. AD8036/AD8037 CMRR vs. Temperature
REV. A
-11-
AD8036/AD8037-Typical Characteristics
24 23 AD8036, VS = SUPPLY CURRENT - mA 22 21 20 19 18 17 -60 AD8037, VS = 5V AD8037, VS = 6V 5V 6V 270 260 AD8036 250 AD8037 240 AD8037 SINK AD8036 SHORT CIRCUIT CURRENT - mA
AD8036, VS =
230 220
SOURCE
210
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE - C
120
140
200 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE - C
120
140
Figure 51. Supply Current vs. Temperature
Figure 54. Short Circuit Current vs. Temperature
-2.50 VS = -2.25 INPUT OFFSET VOLTAGE - mV 6V
4.5 -IB 4.0 AD8036 +IB 3.5 -IB 3.0 AD8037 +IB 2.5 A AD8037 VS = 6V VS = 5V VS = 5V AD8036 INPUT BIAS CURRENT - 140 2.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE - C 120 1.5 -60
-2.00 -1.75 -1.50 -1.25 -1.00 -0.75 -0.50 -60
-40
-20
0 20 40 60 80 100 JUNCTION TEMPERATURE - C
120
140
Figure 52. Input Offset Voltage vs. Temperature
Figure 55. Input Bias Current vs. Temperature
44 40 36 32 28 COUNT 24 20 16 12 8 4 0 -6 -5 -4 -3 -2 -1 0 1 INPUT OFFSET VOLTAGE - mV 2 3 4 FREQ. DIST COUNT 3 WAFER LOTS COUNT = 632
48 44 40 36 32 28 24 20 16 12 8 4 0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 INPUT OFFSET VOLTAGE - mV 0 0.5 FREQ. DIST 3 WAFER LOTS COUNT = 853
Figure 53. AD8036 Input Offset Voltage Distribution
Figure 56. AD8037 Input Offset Voltage Distribution
-12-
REV. A
Clamp Characteristics-AD8036/AD8037
20 15 INPUT ERROR VOLTAGE - mV 10 5 0 -5 -10 -15 -20 -3 VCH = +1V VCH = +2V VCH = +3V AD8036 AD8037 VCL = -3V VCL = -2V VCL = -1V AD8036, ACL = +1 AD8037, ACL = +2
-80 -75
HARMONIC DISTORTION - dBc
-70 -65 -60 -55 -50 -45 -40 -35
AD8037 3RD HARMONIC
AD8037 2ND HARMONIC
AD8036 3RD HARMONIC
AD8036 2ND HARMONIC
AD8036 AD8037
VH VL G +1V -1V +1V +0.5V -0.5V +2V 1.0
-2
-1 0 1 OUTPUT VOLTAGE - Volts
2
3
-30 0.6
0.65 0.7 0.75 0.8 0.85 0.9 0.95 ABSOLUTE VALUE OF OUTPUT VOLTAGE - Volts
Figure 57. Input Error Voltage vs. Clamped Output Voltage
Figure 60. Harmonic Distortion as Output Approaches Clamp Voltage; VO = 2 V p-p, RL = 100 , f = 20 MHz
20 15 10 VH = + 1V VL = - 1V
80 60 40 20 0 -20 -40 -60 -80 -5 IBL IBH POSITIVE IBH, IBL DENOTES CURRENT FLOW INTO CLAMP INPUTS VH, VL
5 0 -5 -10 -15 -20 -1.0
CLAMP INPUT BIAS CURRENT - A
NONLINEARITY - mV
-0.8
-0.6
-0.4 -0.2 0.0 0.2 0.4 INPUT VOLTAGE AV - Volts
0.6
0.8
1.0
-4
-3 -2 -1 0 1 2 3 INPUT CLAMP VOLTAGE (VH ,VL) - Volts
4
5
Figure 58. AD8036/AD8037 Nonlinearity Near Clamp Voltage
Figure 61. AD8036/AD8037 Clamp Input Bias Current vs. Input Clamp Voltage
+2V
+2V
+1V
+1V
0V
0V
REF
REF
Figure 59. AD8036 Clamp Overdrive (2X) Recovery
Figure 62. AD8037 Clamp Overdrive (2X) Recovery
REV. A
-13-
AD8036/AD8037-Clamp Characteristics
0.5 0.4 0.3 0.2 ERROR - % 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 10 20 30 40 50 60 SETTLING TIME - ns 70 80 90 ERROR - % 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 10 20 30 40 50 60 SETTLING TIME - ns 70 80 90
Figure 63. AD8036 Clamp Settling (0.1%), V H = +1 V, VL = -1 V, 2x Overdrive
Figure 66. AD8037 Clamp Settling (0.1%), VH = +0.5 V, VL = -0.5 V, 2x Overdrive
0.5 0.4 0.3 0.2 ERROR - % 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 25 SETTLING TIME - ns 30 35 40 ERROR - %
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 25 SETTLING TIME - ns 30 35 40
Figure 64. AD8036 Clamp Recovery Settling Time (High), from +2x Overdrive to 0 V
Figure 67. AD8037 Clamp Recovery Settling Time (High), from +2 x Overdrive to 0 V
0.5 0.4 0.3 0.2 ERROR - % 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 25 SETTLING TIME - ns 30 35 40 ERROR - %
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 25 SETTLING TIME - ns 30 35 40
Figure 65. AD8036 Clamp Recovery Settling Time (Low), from -2x Overdrive to 0 V
Figure 68. AD8037 Clamp Recovery Settling Time (Low), from -2x Overdrive to 0 V
-14-
REV. A
AD8036/AD8037
THEORY OF OPERATION General
The AD8036 and AD8037 are wide bandwidth, voltage feedback clamp amplifiers. Since their open-loop frequency response follows the conventional 6 dB/octave roll-off, their gain bandwidth product is basically constant. Increasing their closed-loop gain results in a corresponding decrease in small signal bandwidth. This can be observed by noting the bandwidth specification, between the AD8036 (gain of 1) and AD8037 (gain of 2). The AD8036/AD8037 typically maintain 65 degrees of phase margin. This high margin minimizes the effects of signal and noise peaking. While the AD8036 and AD8037 can be used in either an inverting or noninverting configuration, the clamp function will only work in the noninverting mode. As such, this section shows connections only in the noninverting configuration. Applications that require an inverting configuration will be discussed in the Applications section. In applications that do not require clamping, Pins 5 and 8 (respectively VL and VH) may be left floating. See Input Clamp Amp Operation and Applications sections otherwise.
Feedback Resistor Choice
This estimation loses accuracy for gains of +2/-1 or lower due to the amplifier's damping factor. For these "low gain" cases, the bandwidth will actually extend beyond the calculated value (see Closed-Loop BW plots, Figures 15 and 27).
Pulse Response
Unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the AD8036 and AD8037 provide "on demand" current that increases proportionally to the input "step" signal amplitude. This results in slew rates (1200 V/s) comparable to wideband current feedback designs. This, combined with relatively low input noise current (2.1 pA/Hz), gives the AD8036 and AD8037 the best attributes of both voltage and current feedback amplifiers.
Large Signal Performance
The outstanding large signal operation of the AD8036 and AD8037 is due to a unique, proprietary design architecture. In order to maintain this level of performance, the maximum 350 V-MHz product must be observed, (e.g., @ 100 MHz, VO 3.5 V p-p).
Power Supply and Input Clamp Bypassing
The value of the feedback resistor is critical for optimum performance on the AD8036 (gain +1) and less critical as the gain increases. Therefore, this section is specifically targeted at the AD8036. At minimum stable gain (+1), the AD8036 provides optimum dynamic performance with RF = 140 . This resistor acts only as a parasitic suppressor against damped RF oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. This value of RF provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. In fact, for the same reasons, a 100-130 resistor should be placed in series with the positive input for other AD8036 noninverting configurations. The correct connection is shown in Figure 69.
+VS R G = 1+ F RG 100 - 130 VIN RTERM 10 F VH 0.1 F
Adequate power supply bypassing can be critical when optimizing the performance of a high frequency circuit. Inductance in the power supply leads can form resonant circuits that produce peaking in the amplifier's response. In addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 F) will be required to provide the best settling time and lowest distortion. A parallel combination of at least 4.7 F, and between 0.1 F and 0.01 F, is recommended. Some brands of electrolytic capacitors will require a small series damping resistor 4.7 for optimum results. When the AD8036 and AD8037 are used in clamping mode, and a dc voltage is connected to clamp inputs VH and VL, a 0.1 F bypassing capacitor is required between each input pin and ground in order to maintain stability.
Driving Capacitive Loads
AD8036/ AD8037
0.1 F VL -VS RG 10 F RF
VOUT
The AD8036 and AD8037 were designed primarily to drive nonreactive loads. If driving loads with a capacitive component is desired, the best frequency response is obtained by the addition of a small series resistance as shown in Figure 70. The accompanying graph shows the optimum value for RSERIES vs. capacitive load. It is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of RSERIES and CL . For capacitive loads of 6 pF or less, no RSERIES is necessary.
RF RIN
Figure 69. Noninverting Operation
RIN
AD8036/ AD8037
RSERIES RL 1k CL
For general voltage gain applications, the amplifier bandwidth can be closely estimated as: f 3 dB O RF 2 1+ RG
Figure 70. Driving Capacitive Loads
REV. A
-15-
AD8036/AD8037
40
30 R SERIES -
Operation of the AD8036 for negative input voltages and negative clamp levels on VL is similar, with comparator CL controlling S1. Since the comparators see the voltage on the +VIN pin as their common reference level, then the voltage VH and VL are defined as "High" or "Low" with respect to +VIN. For example, if VIN is set to zero volts, VH is open, and VL is +1 V, comparator CL will switch S1 to "C," so the AD8036 will buffer the voltage on VL and ignore +VIN. The performance of the AD8036 and AD8037 closely matches the ideal just described. The comparator's threshold extends from 60 mV inside the clamp window defined by the voltages on VL and VH to 60 mV beyond the window's edge. Switch S1 is implemented with current steering, so that A1's +input makes a continuous transition from say, VIN to VH as the input voltage traverses the comparator's input threshold from 0.9 V to 1.0 V for VH = 1.0 V. The practical effect of these nonidealities is to soften the transition from amplification to clamping modes, without compromising the absolute clamp limit set by the CLAMPIN circuit. Figure 73 is a graph of VOUT vs. VIN for the AD8036 and a typical output clamp amplifier. Both amplifiers are set for G = +1 and VH = +1 V. The worst case error between VOUT (ideally clamped) and VOUT (actual) is typically 18 mV times the amplifier closed-loop gain. This occurs when VIN equals VH (or VL). As VIN goes above and/or below this limit, VOUT will settle to within 5 mV of the ideal value. In contrast, the output clamp amplifier's transfer curve typically will show some compression starting at an input of 0.8 V, and can have an output voltage as far as 200 mV over the clamp limit. In addition, since the output clamp in effect causes the amplifier to operate open loop in clamp mode, the amplifier's output impedance will increase, potentially causing additional errors. The AD8036's and AD8037's CLAMPIN input clamp architecture works only for noninverting or follower applications and, since it operates on the input, the clamp voltage levels VH and VL, and input error limits will be multiplied by the amplifier's
RF 140
20
10 0 5 10 CL- pF 15 20 25
Figure 71. Recommended RSERIES vs. Capacitive Load
INPUT CLAMPING AMPLIFIER OPERATION
The key to the AD8036 and AD8037's fast, accurate clamp and amplifier performance is their unique patent pending CLAMPIN input clamp architecture. This new design reduces clamp errors by more than 10x over previous output clamp based circuits, as well as substantially increasing the bandwidth, precision and versatility of the clamp inputs. Figure 72 is an idealized block diagram of the AD8036 connected as a unity gain voltage follower. The primary signal path comprises A1 (a 1200 V/s, 240 MHz high voltage gain, differential to single-ended amplifier) and A2 (a G = +1 high current gain output buffer). The AD8037 differs from the AD8036 only in that A1 is optimized for closed-loop gains of two or greater. The CLAMPIN section is comprised of comparators CH and CL, which drive switch S1 through a decoder. The unity-gain buffers in series with +VIN, VH , and VL inputs isolate the input pins from the comparators and S1 without reducing bandwidth or precision. The two comparators have about the same bandwidth as A1 (240 MHz), so they can keep up with signals within the useful bandwidth of the AD8036. To illustrate the operation of the CLAMPIN circuit, consider the case where VH is referenced to +1 V, VL is open, and the AD8036 is set for a gain of +1, by connecting its output back to its inverting input through the recommended 140 feedback resistor. Note that the main signal path always operates closed loop, since the CLAMPIN circuit only affects A1's noninverting input. If a 0 V to +2 V voltage ramp is applied to the AD8036's +VIN for the connection just described, VOUT should track +VIN perfectly up to +1 V, then should limit at exactly +1 V as +VIN continues to +2 V. In practice, the AD8036 comes close to this ideal behavior. As the +VIN input voltage ramps from zero to 1 V, the output of the high limit comparator CH starts in the off state, as does the output of CL. When +VIN just exceeds VIN (ideally, by say 1 V, practically by about 18 mV), CH changes state, switching S1 from "A" to "B" reference level. Since the + input of A1 is now connected to VH, further increases in +VIN have no effect on the AD8036's output voltage. In short, the AD8036 is now operating as a unity-gain buffer for the VH input, as any variation in VH, for VH > 1 V, will be faithfully reproduced at VOUT.
-VIN +VIN VH VL +1 +1 +1 CH B C S1 VIN > VH A S1 A1
A2 +1
VOUT
ABC 010
VL VIN VH 1 0 0 VIN < VL CL 001
Figure 72. AD8036/AD8037 Clamp Amp System
-16-
REV. A
AD8036/AD8037
closed-loop gain at the output. For instance, to set an output limit of 1 V for an AD8037 operating at a gain of 3.0, VH and VL would need to be set to +0.333 V and -0.333 V, respectively. The only restriction on using the AD8036's and AD8037's +VIN, VL, VH pins as inputs is that the maximum voltage difference between +VIN and VH or V L should not exceed 6.3 V, and all three voltages be within the supply voltage range. For example, if VL is set at -3 V, then VIN should not exceed +3.3 V.
1.6 VIN
Clamping with Gain
Figure 75 shows an AD8037 configured for a noninverting gain of two. The AD8037 is used in this circuit since it is compensated for gains of two or greater and provides greater bandwidth. In this case, the high clamping level at the output will
VH 0.1 F +5V
0.1 F 130 VH
10 F
AD8036
1.4 OUTPUT VOLTAGE - VOUT VL 0.1 F 0.1 F CLAMP ERROR - 25mV AD8036 1.0 AD8036 0.8 OUTPUT CLAMP AMP CLAMP ERROR - >200mV OUTPUT CLAMP -5V VL RF 140 10 F
VOUT
1.2
Figure 74. Unity Gain Noninverting Clamp
0.6 0.6
0.8
1.0
1.2 1.4 1.6 INPUT VOLTAGE - +VIN
1.8
2.0
occur at 2 x VH and the low clamping level at the output will be 2 x VL. The equations governing the output clamp levels in circuits configured for noninverting gain are: VCH = G x VH VCL = G x VL where: VCH is the high output clamping level VCL is the low output clamping level G is the gain of the amplifier configuration VH is the high input clamping level (Pin 8) VL is the low input clamping level (Pin 5)
VH 0.1 F
Figure 73. Output Clamp Error vs. Input Clamp Error
AD8036/AD8037 APPLICATIONS
The AD8036 and AD8037 use a unique input clamping circuit to perform the clamping function. As a result, they provide the clamping function better than traditional output clamping devices and provide additional flexibility to perform other unique applications. There are, however, some restrictions on circuit configurations; and some calculations need to be performed in order to figure the clamping level, as a result of clamping being performed at the input stage. The major restriction on the clamping feature of the AD8036/ AD8037 is that clamping occurs only when using the amplifiers in the noninverting mode. To clamp in an inverting circuit, an additional inverting gain stage is required. Another restriction is that VH be greater than VL, and that each be within the output voltage range of the amplifier ( 3.9 V). VH can go below ground and VL can go above ground as long as VH is kept higher than VL.
Unity Gain Clamping
*Amplifier offset is assumed to be zero.
+5V
0.1 F 100 VIN 49.9 VH
10 F
AD8037
VL 0.1 F 0.1 F -5V 10 F
VOUT
RG 274
VL
RF 274
The simplest circuit for calculating the clamp levels is a unity gain follower as shown in Figure 74. In this case, the AD8036 should be used since it is compensated for noninverting unity gain. This circuit will clamp at an upper voltage set by VH (the voltage applied to Pin 8) and a lower voltage set by VL (the voltage applied to Pin 5).
Figure 75. Gain of Two Noninverting Clamp
REV. A
-17-
AD8036/AD8037
+5V 806 +5V 0.1 F +5V 0.1 F -0.5V to +0.5V 10F 0.1 F VIN R3 750 49.9 100 VH 10 F 1N5712 100
AD9002
-2V to 0V 49.9 CLAMPING RANGE -2.1V to +0.1V 0.1 F 10 F VIN = -2V TO 0V
AD8037
VL
AD780
2.5V 0.1 F
100 806 R1 499 -5V 0.1 F -5V
SUBSTRATE DIODE
R2 301
0.1 F -5.2V
Figure 76. Gain of Two, Noninverting with Offset AD8037 Driving an AD9002--8-Bit, 125 MSPS A/D Converter
Clamping with an Offset
Some op amp circuits are required to operate with an offset voltage. These are generally configured in the inverting mode where the offset voltage can be summed in as one of the inputs. Since AD8036/AD8037 clamping does not function in the inverting mode, it is not possible to clamp with this configuration. Figure 76 shows a noninverting configuration of an AD8037 that provides clamping and also has an offset. The circuit shows the AD8037 as a driver for an AD9002, an 8-bit, 125 Msps A/D converter and illustrates some of the considerations for using an AD8037 with offset and clamping. The analog input range of the AD9002 is from ground to -2 V. The input should not go more than 0.5 V outside this range in order to prevent disruptions to the internal workings of the A/D and to avoid drawing excess current. These requirements make the AD8037 a prime candidate for signal conditioning. When an offset is added to a noninverting op amp circuit, it is fed in through a resistor to the inverting input. The result is that the op amp must now operate at a closed-loop gain greater than unity. For this circuit a gain of two was chosen which allows the use of the AD8037. The feedback resistor, R2, is set at 301 for optimum performance of the AD8037 at a gain of two. There is an interaction between the offset and the gain, so some calculations must be performed to arrive at the proper values for R1 and R3. For a gain of two the parallel combination of resistors R1 and R3 must be equal to the feedback resistor R2. Thus R1 x R3/R1 + R3 = R2 = 301 The reference used to provide the offset is the AD780 whose output is 2.5 V. This must be divided down to provide the 1 V offset desired. Thus 2.5 V x R1/(R1 + R3) = 1 V When the two equations are solved simultaneously we get R1 = 499 and R3 = 750 (using closest 1% resistor values in all cases). This positive 1 V offset at the input translates to a -1 V offset at the output. The usable input signal swing of the AD9002 is 2 V p-p. This is centered about the -1 V offset making the usable signal range from 0 V to -2 V. It is desirable to clamp the input signal so
that it goes no more than 100 mV outside of this range in either direction. Thus, the high clamping level should be set at +0.1 V and the low clamping level should be set at -2.1 V as seen at the input of the AD9002 (output of AD8037). Because the clamping is done at the input stage of the AD8037, the clamping level as seen at the output is affected by not only the gain of the circuit as previously described, but also by the offset. Thus, in order to obtain the desired clamp levels, VH must be biased at +0.55 V while VL must be biased at -0.55 V. The clamping levels as seen at the output can be calculated by the following: VCH = VOFF + G x VH VCL = VOFF + G x VL Where VOFF is the offset voltage that appears at the output. The resistors used to generate the voltages for VH and VL should be kept to a minimum in order to reduce errors due to clamp bias current. This current is dependent on VH and VL (see Figure 61) and will create a voltage drop across whatever resistance is in series with each clamp input. This extra error voltage is multiplied by the closed-loop gain of the amplifier and can be substantial, especially in high closed-loop gain configurations. A 0.1 F bypass capacitor should be placed between input clamp pins VH and VL and ground to ensure stable operation. The 1N5712 Schottky diode is used for protection from forward biasing the substrate diode in the AD9002 during power-up transients.
Programmable Pulse Generator
The AD8036/AD8037's clamp output can be set accurately and has a well controlled flat level. This along with wide bandwidth and high slew rate make them very well suited for programmable level pulse generators. Figure 77 is a schematic for a pulse generator that can directly accept TTL generated timing signals for its input and generate pulses at the output up to 24 V p-p with 2500 V/s slew rate. The output levels can be programmed to anywhere in the range -12 V to +12 V.
-18-
REV. A
AD8036/AD8037
VH 0.1 F +5V +15V 0.1 F 200 TTLIN 1.3k -15V 0.1 F 0.1 F -5V VL 274 274 150 -15V 0.1 F 604 10 F 10 F 100 VH 10 F 0.1 F 10 F VH VL 10 10
AD8037
VL
100
AD811
PULSE OUT
Figure 77. Programmable Pulse Generator
The circuit uses an AD8037 operating at a gain of two with an AD811 to boost the output to the 12 V range. The AD811 was chosen for its ability to operate with 15 V supplies and its high slew rate. R1 and R2 act as a level shifter to make the TTL signal levels be approximately symmetrical above and below ground. This ensures that both the high and low logic levels will be clamped by the AD8037. For well controlled signal levels in the output pulse, the high and low output levels should result from the clamping action of the AD8037 and not be controlled by either the high or low logic levels passing through a linear amplifier. For good rise and fall times at the output pulse, a logic family with high speed edges should be used. The high logic levels are clamped at two times the voltage at VH , while the low logic levels are clamped at two times the voltage at VL. The output of the AD8037 is amplified by the AD811 operating at a gain of 5. The overall gain of 10 will cause the high output level to be 10 times the voltage at VH, and the low output level to be 10 times the voltage at VL.
High Speed, Full-Wave Rectifier
The circuit is configured as an inverting amplifier with a gain of one. The input drives the inverting amplifier and also directly drives VL, the lower level clamping input. The high level clamping input, VH, is left floating and plays no role in this circuit. When the input is negative, the amplifier acts as a regular unitygain inverting amplifier and outputs a positive signal at the same amplitude as the input with opposite polarity. VL is driven negative by the input, so it performs no clamping action, because the positive output signal is always higher than the negative level driving VL. When the input is positive, the output result is the sum of two separate effects. First, the inverting amplifier multiplies the input by -1 because of its unity-gain inverting configuration. This effectively produces an offset as explained above, but with a dynamic level that is equal to -1 times the input. Second, although the positive input is grounded (through 100 ), the output is clamped at two times the voltage applied to VL (a positive, dynamic voltage in this case). The factor of two is because the noise gain of the amplifier is two. The sum of these two actions results in an output that is equal to unity times the input signal for positive input signals, see Figure 79. For a input/output scope photo with an input signal of 20 MHz and amplitude 1 V, see Figure 80.
INPUT
The clamping inputs are additional inputs to the input stage of the op amp. As such they have an input bandwidth comparable to the amplifier inputs and lend themselves to some unique functions when they are driven dynamically. Figure 78 is a schematic for a full-wave rectifier, sometimes called an absolute value generator. It works well up to 20 MHz and can operate at significantly higher frequencies with some degradation in performance. The distortion performance is significantly better than diode based full-wave rectifiers, especially at high frequencies.
+5V
LOWER CLAMPING LEVEL WITH NO NEG INPUT
0.1 F 100 VH
10 F
FULL WAVE RECTIFIED OUTPUT
AD8037
VL 0.1 F RG 274 VIN RF 274 -5V 10 F
VOUT = VIN
-1
INPUT OUTPUT
LOWER CLAMPING LEVEL
Figure 79. Figure 78. Full-Wave Rectifier
REV. A
-19-
AD8036/AD8037
The modulation signal is applied to both the input of a unity gain inverting amplifier and to VL, the lower clamping input. VH is biased at +0.5 V dc. To understand the circuit operation, it is helpful to first consider a simpler circuit. If both VL and VH were dc biased at -0.5 V and the carrier and modulation inputs driven as above, the output would be a 2 V p-p square wave at the carrier frequency riding on a waveform at the modulating frequency. The inverting input (modulation signal) is creating a varying offset to the 2 V p-p square wave at the output. Both the high and low levels clamp at twice the input levels on the clamps because the noise gain of the circuit is two. When VL is driven by the modulation signal instead of being held at a dc level, a more complicated situation results. The resulting waveform is composed of an upper envelope and a lower envelope with the carrier square wave in between. The upper and lower envelope waveforms are 180 out of phase as in a typical AM waveform. The upper envelope is produced by the upper clamp level being offset by the waveform applied to the inverting input. This offset is the opposite polarity of the input waveform because of the inverting configuration. The lower envelope is produced by the sum of two effects. First, it is offset by the waveform applied to the inverting input as in the case of the simplified circuit above. The polarity of this offset is in the same direction as the upper envelope. Second, the output is driven in the opposite direction of the offset at twice the offset voltage by the modulation signal being applied to VL. This results from the noise gain being equal to two, and since there is no inversion in this connection, it is opposite polarity from the offset. The result at the output for the lower envelope is the sum of these two effects, which produces the lower envelope of an amplitude modulated waveform. See Figure 82.
Figure 80. Full-Wave Rectifier Scope
Thus for either positive or negative input signals, the output is unity times the absolute value of the input signal. The circuit can be easily configured to produce the negative absolute value of the input by applying the input to VH instead of VL. The circuit can get to within about 40 mV of ground during the time when the input crosses zero. This voltage is fixed over a wide frequency range and is a result of the switching between the conventional op amp input and the clamp input. But because there are no diodes to rapidly switch from forward to reverse bias, the performance far exceeds that of diode based full wave rectifiers. The 40 mV offset mentioned can be removed by adding an offset to the circuit. A 27.4 k input resistor to the inverting input will have a gain of 0.01, while changing the gain of the circuit by only 1%. A plus or minus 4 V dc level (depending on the polarity of the rectifier) into this resistor will compensate for the offset. Full wave rectifiers are useful in many applications including AM signal detection, high frequency ac voltmeters and various arithmetic operations.
Amplitude Modulator
In addition to being able to be configured as an amplitude demodulator (AM detector), the AD8037 can also be configured as an amplitude modulator as shown in Figure 81.
VH +5V
0.1 F 100 CARRIER IN VH
10 F
AD8037
VL 0.1 F RG 274 MODULATION IN RF 274 -5V 10 F
AM OUT
Figure 82. AM Waveform
Figure 81. Amplitude Modulator
The depth of modulation can be modified in this circuit by changing the amplitude of the modulation signal. This changes the amplitude of the upper and lower envelope waveforms. The modulation depth can also be changed by changing the dc bias applied to VH . In this case the amplitudes of the upper and lower envelope waveforms stay constant, but the spacing between them changes. This alters the ratio of the envelope amplitude to the amplitude of the overall waveform.
The positive input of the AD8037 is driven with a square wave of sufficient amplitude to produce clamping action at both the high and low levels. This is the higher frequency carrier signal.
-20-
REV. A
AD8036/AD8037
Layout Considerations
VH +VS 1k RF 0.1 F +VS RG -VS
The specified high speed performance of the AD8036 and AD8037 requires careful attention to board layout and component selection. Proper RF design techniques and low pass parasitic component selection are mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed from the area near the input pins to reduce stray capacitance. Chip capacitors should be used for supply and input clamp bypassing (see Figure 83). One end should be connected to the ground plane and the other within 1/8 inch of each power and clamp pin. An additional large (0.47 F-10 F) tantalum electrolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. The feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. Capacitance variations of less than 1 pF at the inverting input will significantly affect high speed performance. Stripline design techniques should be used for long signal traces (greater than about 1 inch). These should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end.
Evaluation Board
IN RT
RS
AD8036/ AD8037
-VS 0.1 F +VS 1k VL -VS
RO VOUT
NONINVERTING CONFIGURATION
+VS OPTIONAL C1 0.01 F C2 0.01 F -VS SUPPLY BYPASSING C3 0.1 F C4 0.1 F C5 10 F C6 10 F
Figure 83. Noninverting Configurations for Evaluation Boards
An evaluation board for both the AD8036 and AD8037 is available that has been carefully laid out and tested to demonstrate that the specified high speed performance of the device can be realized. For ordering information, please refer to the Ordering Guide. The layout of the evaluation board can be used as shown or serve as a guide for a board layout.
Table I.
Component RF RG RO (Nominal) RS RT (Nominal) Small Signal BW (MHz)
+1 140 49.9 130 49.9 240
+2 274 274 49.9 100 49.9 90
AD8036A Gain +10 2 k 221 49.9 100 49.9 10
+100 2 k 20.5 49.9 100 49.9 1.3
+2 274 274 49.9 100 49.9 275
AD8037A Gain +10 +100 2 k 221 49.9 100 49.9 21 2 k 20.5 49.9 100 49.9 3
REV. A
-21-
AD8036/AD8037
Figure 84. Evaluation Board Silkscreen (Top)
Figure 86. Board Layout (Solder Side)
Figure 85. Evaluation Board Silkscreen (Bottom)
Figure 87. Board Layout (Component Side)
-22-
REV. A
AD8036/AD8037
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP (N Package)
0.430 (10.92) 0.348 (8.84)
8 5
0.280 (7.11) 0.240 (6.10)
1 4
PIN 1 0.100 (2.54) BSC 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381) 0.008 (0.204)
8-Lead Plastic SOIC (SO Package)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
8-Lead Cerdip (Q Package)
0.005 (0.13) MIN
8
0.055 (1.4) MAX
5
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) BSC 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.200.(5.08) MAX 0.200 (5.08) 0.125 (3.18)
SEATING 0.023 (0.58) 0.070 (1.78) PLANE 0.014 (0.36) 0.030 (0.76)
15 0
0.015 (0.38) 0.008 (0.20)
REV. A
-23-
PRINTED IN U.S.A.
0.405 (10.29) MAX
0.320 (8.13) 0.290 (7.37)
C1980a-0-9/99

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